Description: 同步计数器和异步计数器在设计时有哪些区别？试用 六进制计数器和一个十进制计数器构成一个六十进制同步计数器。-synchronous and asynchronous counter counter in the design these differences? 6 probation and 229 counters constitute a decimal counter a six decimal synchronous counter. Platform: |
Size: 848 |
Author:sunqionghui |
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Description: 交通灯控制电路 一、 设计任务与要求 1．设计一个十字路口的交通灯控制电路，要求甲车道和乙车道两条交叉道路上的车辆交替 运行，每次通行时间都设为25秒； 2．要求黄灯先亮5秒，才能变换运行车道； 3．黄灯亮时，要求每秒钟闪亮一次 。 二、实验预习要求 1．复习数字系统设计基础。 2．复习多路数据选择器、二进制同步计数器的工作原理。 3．根据交通灯控制系统框图，画出完整的电路图。-a control circuit design tasks and requirements 1. Design a crossroads of traffic lights control circuit, and requested a B lane cross-road of two lanes of traffic on the turn of operation, each time prevailing Set 25 seconds; 2. Asked yellow first-five seconds, can transform running lanes; 3. Bright yellow light, flashing a request per second. Two experimental rehearsal requirements 1. Review of digital systems design basis. 2. Review of Multiple Choice of data, binary synchronous counter to the principle. 3. According to the traffic light control system block diagram to depict the integrity of the circuit. Platform: |
Size: 969 |
Author:刘鹏 |
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Description: 交通灯控制电路 一、 设计任务与要求 1．设计一个十字路口的交通灯控制电路，要求甲车道和乙车道两条交叉道路上的车辆交替 运行，每次通行时间都设为25秒； 2．要求黄灯先亮5秒，才能变换运行车道； 3．黄灯亮时，要求每秒钟闪亮一次 。 二、实验预习要求 1．复习数字系统设计基础。 2．复习多路数据选择器、二进制同步计数器的工作原理。 3．根据交通灯控制系统框图，画出完整的电路图。-a control circuit design tasks and requirements 1. Design a crossroads of traffic lights control circuit, and requested a B lane cross-road of two lanes of traffic on the turn of operation, each time prevailing Set 25 seconds; 2. Asked yellow first-five seconds, can transform running lanes; 3. Bright yellow light, flashing a request per second. Two experimental rehearsal requirements 1. Review of digital systems design basis. 2. Review of Multiple Choice of data, binary synchronous counter to the principle. 3. According to the traffic light control system block diagram to depict the integrity of the circuit. Platform: |
Size: 1024 |
Author:刘鹏 |
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Description: 按键输入模块（key）：
--可编程延时发生器（数字同步机）的前端输入模块：0－9十个数字键按键输入模块原型
--前端模块：消抖
--对i0－i9十个输入端的两点要求：
--（1）输入端要保证一段时间的稳定高电平
--（2）不能同时按下两个或多于两个的键
--后级模块：1、编码；2、可变模计数器
--编码模块：8线－4线（0－8 BCD码）
--可变模计数器模块：以编码模块输出的32位BCD码为模值-button input module (key) :-- programmable delay generator (digital synchronous machine) the front-end input module : 0-2-9 10 numeric keys keys input module prototype-- front-end module : Consumers quiver-- the domain-Makes 10 input of the two requirements :-- (a) input to ensure a period of stability to I-- (2) can not be pressed together two or more two keys-- after class modules : one, coding; 2, variable Die counter-- Coding modules : 8-to-four (0-8 BCD)-- Variable Mode counter modules : coding module output to the 32 BCD value to Die Platform: |
Size: 2048 |
Author:汪汪 |
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Description: 同步计数器和异步计数器在设计时有哪些区别？试用 六进制计数器和一个十进制计数器构成一个六十进制同步计数器。-synchronous and asynchronous counter counter in the design these differences? 6 probation and 229 counters constitute a decimal counter a six decimal synchronous counter. Platform: |
Size: 1024 |
Author:sunqionghui |
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Description: 基于fpga和sopc的用VHDL语言编写的EDA含异步清0和同步时钟使能的加法计数器-FPGA and SOPC based on the use of VHDL language with asynchronous EDA-ching 0 and synchronous clock so that the adder counter Platform: |
Size: 34816 |
Author:多幅撒 |
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Description: 几个VHDL的例子，供大家参考，包括寄存器的设计，同步二进制计数器的设计，时钟计数器的设计等，个人觉得很有用处-Several examples of VHDL for reference, including the register of designs, synchronous binary counter design, the design of the clock counter, personal feel that is very useful Platform: |
Size: 168960 |
Author:钱 |
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Description: 异步复位、同步置数的四位二进制计数器的VHDL源文件-Asynchronous reset, synchronous purchase the number of binary counter 4 of the VHDL source files Platform: |
Size: 1024 |
Author:chenwen |
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Description: 这是同步十进制计数器的源程序，有需要的同学可以参照一下！-This is a source synchronous decimal counter, needy students can refer to you! Platform: |
Size: 33792 |
Author:逗号 |
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Description: Ripple Carry Counter. the synchronous version of Ripple Counter. a bit less fasr version the ripple counter but a synchronmous one that will work well on FPGA. wrriten in behavioral VHDL. Platform: |
Size: 20480 |
Author:avi |
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Description: vhdl,无进位同步计数器，完成6进制加，输出6进制序列数-vhdl, non-binary synchronous counter to complete the six binary Canada, output 6, the number of binary sequences Platform: |
Size: 37888 |
Author:王晓虎 |
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Description: 可加载的同步四位计数器，异步置位，由控制键控制向下或者向下计数。计数状态由七位数码管显示。-4 synchronous loadable counter, an asynchronous set, controlled by the control key down, or down the count. Count the state from the seven digital tube display. Platform: |
Size: 243712 |
Author:心晨 |
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Description: 设计一个采用数字电路实现,对时,分,秒.数字显示的计时装置,周期为24小时，显示满刻度为23时59分59秒，并具有校时功能和报时功能的数字电子钟。电路主要采用中规模集成电路.本系统的设计电路由脉冲逻辑电路模块、时钟脉冲模块、时钟译码显示电路模块、整电报时模块、校时模块等部分组成。采用电池作电源，采用低功耗的芯片及液晶显示器，发生器使用石英晶振、计数振荡器CD4060及双D触发器74LS74，计数器采用同步双十进制计数器74LS160，锁存译码器是74LS248，整电报时电路用74LS74，74LS32及扬声器构成。-Design a digital circuit, on the hours, minutes, seconds. Figures show that the timing device, 24-hour period, indicating full scale is 23:59:59 and the time with school functions and timekeeping functions of digital electronic clock. Scale integrated circuits used in the main circuit. The design of this system by the pulse logic circuit module, clock module, the clock display circuit decoding module, when the entire cable module, the campus module components. Using a battery powered, low-power chips and liquid crystal display generator using a quartz crystal oscillator, count of CD4060 oscillator and two D flip-flop 74LS74, two-decimal counter synchronous counter 74LS160, latch decoder is the 74LS248, the whole When telegraph circuits 74LS74, 74LS32 and loudspeaker Platform: |
Size: 449536 |
Author:张龙 |
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Description: 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features:
The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered.
The counter is with an asynchronous reset that assigns a specific initial value for counting.
The counter is with a synchronous data load control input for a new value of counting and an enable control input for allowing the up and down counting. The load control input has a priority over the enable control input. This implies that when the load operation is in process the counter operation is prohibited.
Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER, may be used. Platform: |
Size: 1024 |
Author:fjmwu |
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Description: 两种方法实现的同步计数器 （包括例化的），提供全部代码。-Synchronous counter in two ways (including the example of), provided all the code. Platform: |
Size: 896000 |
Author:DongWu |
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Description: 8位上下同步计数器 适宜小型练手操作 易于理解(an 8-bit up and down synchronous counter in VHDL with the following
features:
(1) The same ports are used for signals to be inputted and outputted. The ports are
bi-directionally buffered (three-state).
(2) The counter is with an asynchronous reset that assigns a specific initial value
for counting.
(3) The counter is with a synchronous data load control input for a new value of
counting and an enable control input for allowing the up and down counting.
The load control input has a priority over the enable control input. This
implies that when the load operation is in process the counter operation is
prohibited.
(4) Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER,
may be used) Platform: |
Size: 1014784 |
Author:名之联 |
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